library verilog;
use verilog.vl_types.all;
entity Converter is
    generic(
        pHi             : integer := 3;
        pPad            : integer := 0
    );
    port(
        OutBus          : out    vl_logic_vector;
        InBus           : in     vl_logic_vector;
        Enable          : in     vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of pHi : constant is 1;
    attribute mti_svvh_generic_type of pPad : constant is 1;
end Converter;
